1. Field of the Invention
The present invention relates to a semiconductor storage device and to a method for manufacturing the same. More particularly, the present invention relates to a nonvolatile memory in which a ferroelectric is used for a gate of a transistor so as to directly control a current flowing between a source and a drain, and to a method for manufacturing the same.
2. Description of the Related Art
Semiconductor storage devices are classified into a volatile memory capable of retaining data only when electric power is on and a nonvolatile memory capable of retaining data even when electric power is off. Examples of the volatile memory include a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory), while examples of the nonvolatile memory include a mask ROM (Mask Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), and an EEPROM (Electrically Erasable Programmable Read Only Memory).
Among these nonvolatile memories, an EPROM and an EEPROM are ROMs which can rewrite the memory contents like RAMs, and generally have an MOS-FET (MOS field-effect transistor) structure in which a floating gate is interposed between a control gate and a channel. In an EPROM, an erasing operation is performed by irradiation with ultraviolet rays so as to eject carriers from the inside of a floating gate, while a writing operation is performed by utilizing hot electrons, which are generated by application of a high voltage between a control gate and a drain and then remain inside the floating gate. In an EEPROM, an erasing operation can be carried out without irradiation with ultraviolet rays.
The above-described floating gate type MOS-FET, however, requires a time of the order of msec. and a high electric field of the order of 10.sup.7 V/cm for writing and erasing operations. Accordingly, unlike generally used DRAMs, an EEPROM cannot perform writing and erasing operations in the same cycle, and further, requires a power source of a high voltage.
There have been recently developed FRAMs (Ferroelectric Random Access Memories) most of which have a structure using a ferroelectric capacitor in place of the capacitor in a DRAM (see Japanese Patent Application Laying-open No. 113,496/1990). In an FRAM, writing, erasing, and reading operations involve each a polarization inversion of a ferroelectric, thus posing a problem of fatigue of the ferroelectric. Moreover, any one of these operations takes about 100 nsec. since they involve electric charging and discharging of the ferroelectric capacitor. Furthermore, it is necessary to separately dispose a transistor and a capacitor. This is disadvantageous in reducing an area of the device.
In order to solve the aforementioned problems, a semiconductor storage device having a structure in which an epitaxial oxide film and a ferroelectric thin film are laminated on a gate of a transistor has been proposed in Japanese Patent Application Laying-open No. 97,452/1994. Although a nonvolatile memory which operates at a high speed, suffers from little fatigue of a ferroelectric and is suitable for an area reduction could be provided, there arise problems from the standpoints of reproducibility and stability among various characteristics of a gate of a transistor, thus making it difficult to enhance a throughput upon manufacture. This is because it is difficult to control an interface between an Si substrate and a ferroelectric thin film and because polarization of a ferroelectric is canceled by injection of carriers from the Si substrate into the ferroelectric.